1. Technical Field
The present invention relates to field effect devices having non-volatile behavior as a result of control structures having nanotube components and to methods of forming such devices.
2. Discussion of Related Art
Semiconductor MOSFET transistors are ubiquitous in modern electronics. These field effect devices possess the simultaneous qualities of bistability, high switching speed, low power dissipation, high-reliability, and scalability to very small dimensions. One feature not typical of such MOSFET-based circuits is the ability to retain a digital state (i.e. memory) in the absence of applied power; that is, the digital state is volatile.
FIG. 1 depicts a prior art field effect transistor 10. The transistor 10 includes a gate node 12, a drain node 14, and a source node 18. Typically, the gate node 12 is used to control the device. Specifically, by applying an adequate voltage to the gate node 12 an electric field is caused that creates a conductive path between the drain 14 and source 18. In this sense, the transistor is referred to as switching on.
Currently, most memory storage devices utilize a wide variety of energy dissipating devices which employ the confinement of electric or magnetic fields within capacitors or inductors respectively. Examples of state of the art circuitry used in memory storage include FPGA, CPLD, ASIC, CMOS, ROM, PROM, EPROM, EEPROM, DRAM, MRAM and FRAM, as well as dissipationless trapped magnetic flux in a superconductor and actual mechanical switches, such as relays.
An FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device) is a programmable logic device (PLD), a programmable logic array (PLA), or a programmable array logic (PAL) with a high density of gates, containing up to hundreds of thousands of gates with a wide variety of possible architectures. The ability to modulate (i.e. effectively to open and close) electrical circuit connections on an IC (i.e. to program and reprogram) is at the heart of the FPGA (Field programmable gate array) concept.
An ASIC (Application Specific Integrated Circuit) chip is custom designed (or semi-custom designed) for a specific application rather than a general-purpose chip such as a microprocessor. The use of ASICs can improve performance over general-purpose CPUs, because ASICs are “hardwired” to do a specific job and are not required to fetch and interpret stored instructions.
Important characteristics for a memory cell in electronic device are low cost, nonvolatility, high density, low power, and high speed. Conventional memory solutions include Read Only Memory (ROM), Programmable Read only Memory (PROM), Electrically Programmable Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM).
ROM is relatively low cost but cannot be rewritten. PROM can be electrically programmed but with only a single write cycle. EPROM (Electrically-erasable programmable read-only memories) has read cycles that are fast relative to ROM and PROM read cycles, but has relatively long erase times and reliability only over a few iterative read/write cycles. EEPROM (or “Flash”) is inexpensive, and has low power consumption but has long write cycles (ms) and low relative speed in comparison to DRAM or SRAM. Flash also has a finite number of read/write cycles leading to low long-term reliability. ROM, PROM, EPROM and EEPROM are all non-volatile, meaning that if power to the memory is interrupted the memory will retain the information stored in the memory cells.
DRAM (dynamic random access memory) stores charge on capacitors but must be electrically refreshed every few milliseconds complicating system design by requiring separate circuitry to “refresh” the memory contents before the capacitors discharge. SRAM does not need to be refreshed and is fast relative to DRAM, but has lower density and is more expensive relative to DRAM. Both SRAM and DRAM are volatile, meaning that if power to the memory is interrupted the memory will lose the information stored in the memory cells.
Consequently, existing technologies are either non-volatile but are not randomly accessible and have low density, high cost, and limited ability to allow multiple writes with high reliability of the circuit's function, or they are volatile and complicate system design or have low density. Some emerging technologies have attempted to address these shortcomings.
For example, magnetic RAM (MRAM) or ferromagnetic RAM (FRAM) utilizes the orientation of magnetization or a ferromagnetic region to generate a nonvolatile memory cell. MRAM utilizes a magnetoresistive memory element involving the anisotropic magnetoresistance or giant magnetoresistance of ferromagnetic materials yielding nonvolatility. Both of these types of memory cells have relatively high resistance and low-density. A different memory cell based upon magnetic tunnel junctions has also been examined but has not led to large-scale commercialized MRAM devices. FRAM uses circuit architecture similar to DRAM but which uses a thin film ferroelectric capacitor. This capacitor is purported to retain its electrical polarization after an externally applied electric field is removed yielding a nonvolatile memory. FRAM suffers from a large memory cell size, and it is difficult to manufacture as a large-scale integrated component. See U.S. Pat. Nos. 4,853,893; 4,888,630; 5,198,994, 6,048,740; and 6,044,008.
Another technology having non-volatile memory is phase change memory. This technology stores information via a structural phase change in thin-film alloys incorporating elements such as selenium or tellurium. These alloys are purported to remain stable in both crystalline and amorphous states allowing the formation of a bi-stable switch. While the nonvolatility condition is met, this technology appears to suffer from slow operations, difficulty of manufacture and poor reliability and has not reached a state of commercialization. See U.S. Pat. Nos. 3,448,302; 4,845,533; 4,876,667; and 6,044,008.
Wire crossbar memory (MWCM) has also been proposed. See U.S. Pat. Nos. 6,128,214; 6,159,620; and 6,198,655. These memory proposals envision molecules as bi-stable switches. Two wires (either a metal or semiconducting type) have a layer of molecules or molecule compounds sandwiched in between. Chemical assembly and electrochemical oxidation or reduction are used to generate an “ON” or “OFF” state. This form of memory requires highly specialized wire junctions and may not retain non-volatilely owing to the inherent instability found in redox processes.
Recently, memory devices have been proposed which use nanoscopic wires, such as single-walled carbon nanotubes, to form crossbar junctions to serve as memory cells. See WO 01/03208, Nanoscopic Wire-Based Devices, Arrays, and Methods of Their Manufacture; and Thomas Rueckes et al., “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing,” Science, vol. 289, pp. 94–97, 7 Jul., 2000. These devices are sometimes referred to herein as “nanotube wire crossbar memories (NTWCMs).” Under these proposals, individual single-walled nanotube wires suspended over other wires define memory cells. Electrical signals are written to one or both wires to cause them to physically attract or repel relative to one another. Each physical state (i.e., attracted or repelled wires) corresponds to an electrical state. Repelled wires are an open circuit junction. Attracted wires are a closed state forming a rectified junction. When electrical power is removed from the junction, the wires retain their physical (and thus electrical) state thereby forming a non-volatile memory cell.
The NTWCM proposals to date rely on directed grown or chemical self-assembly techniques to grow the individual nanotubes needed for the memory cells. These techniques are now believed to be difficult to employ at commercial scales using modern technology. Moreover, they may contain inherent limitations such as the length of the nanotubes that may be grown reliably using these techniques, and it may be difficult to control the statistical variance of geometries of nanotube wires so grown.
The ideal memory for at least some purposes is one which would offer low cost per bit, high density, fast random access, read/write cycle times of equal duration, low power consumption, operation over a wide temperature range, a single low-voltage power supply, with a high degree of radiation tolerance. The non-volatile memory cell described herein offers high speed read, but also high speed write (nanosecond) versus the slow (microsecond and millisecond) write time of EEPROM and FLASH EEPROM type of memories. The memory is much denser than conventional SRAM because it has two device, nanotube (NT) and 3 array line structure, and offers competitive performance. The density is less than that of DRAM cells, however, the product offers nondestructive readout (NDRO) operation and volatility.